Combined CVS commit logs for the files of the Elphel projects .
Updated: 6 min 25 sec ago
[fpga] By elphel: Implemented clock phase control in the header file
elphel committed changes to the Elphel project fpga CVS:
Implemented clock phase control in the header file
Implemented clock phase control in the header file
- Modified mcontr_frame_rd.v rev1.3 - added 20 lines, removed 9 lines
[fpga] By elphel: Implemented clock phase control in the header file, added output
elphel committed changes to the Elphel project fpga CVS:
Implemented clock phase control in the header file, added output
Implemented clock phase control in the header file, added output
- Modified mcontr_frame_wr.v rev1.3 - added 22 lines, removed 6 lines
[fpga] By elphel: added missing register declaration
elphel committed changes to the Elphel project fpga CVS:
added missing register declaration
added missing register declaration
- Modified mcontr_cmd.v rev1.2 - added one line, removed none
[fpga] By elphel: provided additional outputs, fixed dqs_re timing
elphel committed changes to the Elphel project fpga CVS:
provided additional outputs, fixed dqs_re timing
provided additional outputs, fixed dqs_re timing
- Modified mcontr_8chn.v rev1.2 - added 21 lines, removed 4 lines
[fpga] By elphel: Replaced library element nonexestent in Spartan3 with generic behavioral module
elphel committed changes to the Elphel project fpga CVS:
Replaced library element nonexestent in Spartan3 with generic behavioral module
Replaced library element nonexestent in Spartan3 with generic behavioral module
- Modified macros333.v rev1.2 - added 29 lines, removed 2 lines
[fpga] By elphel: comment syntax error
elphel committed changes to the Elphel project fpga CVS:
comment syntax error
comment syntax error
- Modified fdct_1d.v rev1.4 - added one line, removed one line
[fpga] By elphel: New FPGA pinout for rev B
elphel committed changes to the Elphel project fpga CVS:
New FPGA pinout for rev B
New FPGA pinout for rev B
- Modified x333.v rev1.1 - added 6 lines, removed 2 lines
[fpga] By elphel: initial release, module combining all the Theora encoding
elphel committed changes to the Elphel project fpga CVS:
initial release, module combining all the Theora encoding
initial release, module combining all the Theora encoding
- Modified compressor_all.v rev1.1 - added none, removed none
[fpga] By elphel: Initial release of the files, modified from original version for 313/333 cameras working in JPEG mode
elphel committed changes to the Elphel project fpga CVS:
Initial release of the files, modified from original version for 313/333 cameras working in JPEG mode
Initial release of the files, modified from original version for 313/333 cameras working in JPEG mode
- Modified color_proc333t.v rev1.1 - added none, removed none
- Modified csconvert333.v rev1.1 - added none, removed none
- Modified defines333.vh rev1.1 - added none, removed none
- Modified dma_fifo333.v rev1.1 - added none, removed none
- Modified interrupts333t.v rev1.1 - added none, removed none
- Modified ioports333t.v rev1.1 - added none, removed none
- Modified sdram_phase.v rev1.1 - added none, removed none
- Modified sensdcclk333.v rev1.1 - added none, removed none
- Modified sensorpix333t.v rev1.1 - added none, removed none
[fpga] By elphel: provided "done" output
elphel committed changes to the Elphel project fpga CVS:
provided "done" output
provided "done" output
- Modified compressor_two.v rev1.2 - added 5 lines, removed 2 lines
[fpga] By elphel: Implemented clock phase control in the header file, reduced block RAM width to 18 (from 36) to resolve conflicts with embedded multipliers
elphel committed changes to the Elphel project fpga CVS:
Implemented clock phase control in the header file, reduced block RAM width to 18 (from 36) to resolve conflicts with embedded multipliers
Implemented clock phase control in the header file, reduced block RAM width to 18 (from 36) to resolve conflicts with embedded multipliers
- Modified compressor_one.v rev1.3 - added 114 lines, removed 12 lines
[fpga] By elphel: Implemented clock phase control in the header file
elphel committed changes to the Elphel project fpga CVS:
Implemented clock phase control in the header file
Implemented clock phase control in the header file
- Modified channel2.v rev1.2 - added 16 lines, removed 6 lines
[fpga] By elphel: added "done" output
elphel committed changes to the Elphel project fpga CVS:
added "done" output
added "done" output
- Modified bit_packager.v rev1.2 - added 6 lines, removed one line
[fpga] By elphel: test fixture and data files for simulating compressor_two
elphel committed changes to the Elphel project fpga CVS:
test fixture and data files for simulating compressor_two
test fixture and data files for simulating compressor_two
- Modified compressor_two.tf rev1.1 - added none, removed none
- Modified hufftab80.dat rev1.1 - added none, removed none
- Modified tokens12_1st.dat rev1.1 - added none, removed none
[fpga] By elphel: test fixture for bit_packager.v
elphel committed changes to the Elphel project fpga CVS:
test fixture for bit_packager.v
test fixture for bit_packager.v
- Modified bit_packager.tf rev1.1 - added none, removed none
[fpga] By elphel: initial release of compressor_two that gets 12-bit "pore-tokens" from the frame memory in coded order, encodes them using Huffman tables and prepares for DMA output
elphel committed changes to the Elphel project fpga CVS:
initial release of compressor_two that gets 12-bit "pore-tokens" from the frame memory in coded order, encodes them using Huffman tables and prepares for DMA output
initial release of compressor_two that gets 12-bit "pore-tokens" from the frame memory in coded order, encodes them using Huffman tables and prepares for DMA output
- Modified bit_packager.v rev1.1 - added none, removed none
- Modified token_encode.v rev1.1 - added none, removed none
[fpga] By elphel: bug fixes to rev 03330025
elphel committed changes to the Elphel project fpga CVS:
bug fixes to rev 03330025
bug fixes to rev 03330025
- Modified compressor_two.v rev1.1 - added 9 lines, removed one line
[fpga] By elphel: data files for simulatin compressor_one
elphel committed changes to the Elphel project fpga CVS:
data files for simulatin compressor_one
data files for simulatin compressor_one
- Modified acdcscale.dat rev1.1 - added none, removed none
- Modified bms.dat rev1.1 - added none, removed none
[fpga] By elphel: several small universal modules
elphel committed changes to the Elphel project fpga CVS:
several small universal modules
several small universal modules
- Modified macros333.v rev1.1 - added none, removed none
[fpga] By elphel: removed obsolete comment
elphel committed changes to the Elphel project fpga CVS:
removed obsolete comment
removed obsolete comment
- Modified mcontr_tok_rd.v rev1.2 - added one line, removed one line