Combined CVS commit logs for the files of the Elphel projects .
Updated: 7 min 45 sec ago
[fpga] By elphel: moved table address strobe 1 cycle...
elphel committed changes to the Elphel project fpga CVS:
moved table address strobe 1 cycle added debug signals
moved table address strobe 1 cycle added debug signals
- Modified compressor_one.v rev1.6 - added 16 lines, removed 2 lines
[fpga] By elphel: comments updated
elphel committed changes to the Elphel project fpga CVS:
comments updated
comments updated
- Modified channel3.v rev1.3 - added one line, removed one line
[fpga] By elphel: not used anymore
elphel committed changes to the Elphel project fpga CVS:
not used anymore
not used anymore
- Modified dma_cntrl333.v rev1.2 - added none, removed none
[fpga] By elphel: fixed bug (signal between different clock domains) and added new status bit for troubleshooting
elphel committed changes to the Elphel project fpga CVS:
fixed bug (signal between different clock domains) and added new status bit for troubleshooting
fixed bug (signal between different clock domains) and added new status bit for troubleshooting
- Modified mcontr_8chn.v rev1.6 - added 40 lines, removed 2 lines
- Modified x333.v rev1.7 - added 6 lines, removed 3 lines
[fpga] By elphel: restored lost status bit that indicates that refresh is running - a way to find out that SDRAM is initialized
elphel committed changes to the Elphel project fpga CVS:
restored lost status bit that indicates that refresh is running - a way to find out that SDRAM is initialized
restored lost status bit that indicates that refresh is running - a way to find out that SDRAM is initialized
- Modified mcontr_8chn.v rev1.5 - added 5 lines, removed 3 lines
- Modified x333.v rev1.6 - added 46 lines, removed 44 lines
[fpga] By elphel: simulation bug fix
elphel committed changes to the Elphel project fpga CVS:
simulation bug fix
simulation bug fix
- Modified compressor_two.v rev1.5 - added one line, removed one line
[fpga] By elphel: chip pinout on the model 333 PCB and timimng constraints
elphel committed changes to the Elphel project fpga CVS:
chip pinout on the model 333 PCB and timimng constraints
chip pinout on the model 333 PCB and timimng constraints
- Modified x333.ucf rev1.1 - added none, removed none
[fpga] By elphel: new rev number, made changes needed for moving some modules to different clock phases
elphel committed changes to the Elphel project fpga CVS:
new rev number, made changes needed for moving some modules to different clock phases
new rev number, made changes needed for moving some modules to different clock phases
- Modified x333.v rev1.5 - added 14 lines, removed 2 lines
[fpga] By elphel: added possibility to save generated tables and data fro comparison wity the actual hardware
elphel committed changes to the Elphel project fpga CVS:
added possibility to save generated tables and data fro comparison wity the actual hardware
added possibility to save generated tables and data fro comparison wity the actual hardware
- Modified x333t.tf rev1.3 - added 150 lines, removed 42 lines
- Modified x333t_tasks.tf rev1.3 - added 296 lines, removed 53 lines
[fpga] By elphel: bug fix, reduced table write data width, moved clock phase
elphel committed changes to the Elphel project fpga CVS:
bug fix, reduced table write data width, moved clock phase
bug fix, reduced table write data width, moved clock phase
- Modified token_encode.v rev1.2 - added 25 lines, removed 4 lines
[fpga] By elphel: changes caused by spreading modules between clock phases to reduce possible ground bounce and interference (channel 7 - read tokens from SDRAM moved)
elphel committed changes to the Elphel project fpga CVS:
changes caused by spreading modules between clock phases to reduce possible ground bounce and interference (channel 7 - read tokens from SDRAM moved)
changes caused by spreading modules between clock phases to reduce possible ground bounce and interference (channel 7 - read tokens from SDRAM moved)
- Modified mcontr_8chn.v rev1.4 - added 22 lines, removed 7 lines
[fpga] By elphel: changes caused by spreading modules between clock phases to reduce possible ground bounce and interference
elphel committed changes to the Elphel project fpga CVS:
changes caused by spreading modules between clock phases to reduce possible ground bounce and interference
changes caused by spreading modules between clock phases to reduce possible ground bounce and interference
- Modified mcontr_tok_rd.v rev1.6 - added 20 lines, removed 8 lines
[fpga] By elphel: just note in comments to verify the DCT pipe after changing clock phases
elphel committed changes to the Elphel project fpga CVS:
just note in comments to verify the DCT pipe after changing clock phases
just note in comments to verify the DCT pipe after changing clock phases
- Modified compressor_one.v rev1.5 - added 2 lines, removed one line
[fpga] By elphel: changes caused by spreading modules between clock phases to reduce possible ground bounce and interference
elphel committed changes to the Elphel project fpga CVS:
changes caused by spreading modules between clock phases to reduce possible ground bounce and interference
changes caused by spreading modules between clock phases to reduce possible ground bounce and interference
- Modified compressor_two.v rev1.4 - added 82 lines, removed 26 lines
[fpga] By elphel: changes caused by spreading modules between clock phases to reduce possible ground bounce and interference
elphel committed changes to the Elphel project fpga CVS:
changes caused by spreading modules between clock phases to reduce possible ground bounce and interference
changes caused by spreading modules between clock phases to reduce possible ground bounce and interference
- Modified compressor_all.v rev1.5 - added 33 lines, removed 8 lines
[fpga] By elphel: bug fix (found during hardware testing)
elphel committed changes to the Elphel project fpga CVS:
bug fix (found during hardware testing)
bug fix (found during hardware testing)
- Modified channel2.v rev1.3 - added 14 lines, removed 7 lines
[fpga] By elphel: bug fix
elphel committed changes to the Elphel project fpga CVS:
bug fix
bug fix
- Modified csconvert333.v rev1.2 - added 2 lines, removed one line
[fpga] By elphel: fixed bug found durin simulation of all the design together
elphel committed changes to the Elphel project fpga CVS:
fixed bug found durin simulation of all the design together
fixed bug found durin simulation of all the design together
- Modified reorder_hilbert.v rev1.4 - added 2 lines, removed one line
[fpga] By elphel: increased the delay from 64 to 65 cycles to fix the bug found during overall simulation
elphel committed changes to the Elphel project fpga CVS:
increased the delay from 64 to 65 cycles to fix the bug found during overall simulation
increased the delay from 64 to 65 cycles to fix the bug found during overall simulation
- Modified pack_tokens.v rev1.3 - added 14 lines, removed 6 lines
[fpga] By elphel: bug fixes durinmg overall simulation
elphel committed changes to the Elphel project fpga CVS:
bug fixes durinmg overall simulation
bug fixes durinmg overall simulation
- Modified mcontr_tok_wr.v rev1.4 - added 5 lines, removed 2 lines