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Combined CVS commit logs for the files of the Elphel projects .
Updated: 19 min 52 sec ago

[fpga] By elphel: moved table address strobe 1 cycle...

Mon, 01/17/2005 - 10:28
elphel committed changes to the Elphel project fpga CVS:
moved table address strobe 1 cycle added debug signals

[fpga] By elphel: comments updated

Mon, 01/17/2005 - 10:26
elphel committed changes to the Elphel project fpga CVS:
comments updated

[fpga] By elphel: not used anymore

Sun, 01/16/2005 - 15:12
elphel committed changes to the Elphel project fpga CVS:
not used anymore

[fpga] By elphel: fixed bug (signal between different clock domains) and added new status bit for troubleshooting

Sun, 01/16/2005 - 13:34
elphel committed changes to the Elphel project fpga CVS:
fixed bug (signal between different clock domains) and added new status bit for troubleshooting

[fpga] By elphel: restored lost status bit that indicates that refresh is running - a way to find out that SDRAM is initialized

Sun, 01/16/2005 - 02:08
elphel committed changes to the Elphel project fpga CVS:
restored lost status bit that indicates that refresh is running - a way to find out that SDRAM is initialized

[fpga] By elphel: simulation bug fix

Sun, 01/16/2005 - 01:21
elphel committed changes to the Elphel project fpga CVS:
simulation bug fix

[fpga] By elphel: chip pinout on the model 333 PCB and timimng constraints

Sun, 01/16/2005 - 00:13
elphel committed changes to the Elphel project fpga CVS:
chip pinout on the model 333 PCB and timimng constraints

[fpga] By elphel: new rev number, made changes needed for moving some modules to different clock phases

Sat, 01/15/2005 - 23:47
elphel committed changes to the Elphel project fpga CVS:
new rev number, made changes needed for moving some modules to different clock phases

[fpga] By elphel: added possibility to save generated tables and data fro comparison wity the actual hardware

Sat, 01/15/2005 - 23:46
elphel committed changes to the Elphel project fpga CVS:
added possibility to save generated tables and data fro comparison wity the actual hardware

[fpga] By elphel: bug fix, reduced table write data width, moved clock phase

Sat, 01/15/2005 - 23:44
elphel committed changes to the Elphel project fpga CVS:
bug fix, reduced table write data width, moved clock phase

[fpga] By elphel: changes caused by spreading modules between clock phases to reduce possible ground bounce and interference (channel 7 - read tokens from SDRAM moved)

Sat, 01/15/2005 - 23:42
elphel committed changes to the Elphel project fpga CVS:
changes caused by spreading modules between clock phases to reduce possible ground bounce and interference (channel 7 - read tokens from SDRAM moved)

[fpga] By elphel: changes caused by spreading modules between clock phases to reduce possible ground bounce and interference

Sat, 01/15/2005 - 23:42
elphel committed changes to the Elphel project fpga CVS:
changes caused by spreading modules between clock phases to reduce possible ground bounce and interference

[fpga] By elphel: just note in comments to verify the DCT pipe after changing clock phases

Sat, 01/15/2005 - 23:39
elphel committed changes to the Elphel project fpga CVS:
just note in comments to verify the DCT pipe after changing clock phases

[fpga] By elphel: changes caused by spreading modules between clock phases to reduce possible ground bounce and interference

Sat, 01/15/2005 - 23:39
elphel committed changes to the Elphel project fpga CVS:
changes caused by spreading modules between clock phases to reduce possible ground bounce and interference

[fpga] By elphel: changes caused by spreading modules between clock phases to reduce possible ground bounce and interference

Sat, 01/15/2005 - 23:37
elphel committed changes to the Elphel project fpga CVS:
changes caused by spreading modules between clock phases to reduce possible ground bounce and interference

[fpga] By elphel: bug fix (found during hardware testing)

Sat, 01/15/2005 - 23:35
elphel committed changes to the Elphel project fpga CVS:
bug fix (found during hardware testing)

[fpga] By elphel: bug fix

Mon, 01/10/2005 - 13:54
elphel committed changes to the Elphel project fpga CVS:
bug fix

[fpga] By elphel: fixed bug found durin simulation of all the design together

Sat, 01/08/2005 - 00:53
elphel committed changes to the Elphel project fpga CVS:
fixed bug found durin simulation of all the design together

[fpga] By elphel: increased the delay from 64 to 65 cycles to fix the bug found during overall simulation

Sat, 01/08/2005 - 00:52
elphel committed changes to the Elphel project fpga CVS:
increased the delay from 64 to 65 cycles to fix the bug found during overall simulation

[fpga] By elphel: bug fixes durinmg overall simulation

Sat, 01/08/2005 - 00:50
elphel committed changes to the Elphel project fpga CVS:
bug fixes durinmg overall simulation

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