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Combined CVS commit logs for the files of the Elphel projects .
Updated: 20 min ago

[fpga] By elphel: moved 2's complement -> {sign,abs} conversion on the output here from the module above

Tue, 01/25/2005 - 17:56
elphel committed changes to the Elphel project fpga CVS:
moved 2's complement -> {sign,abs} conversion on the output here from the module above

[fpga] By elphel: Two bugs were discovered and fixed while testing the output data with a standard decoder, both related to replacing the predicted value with one of the 3 neighbours (L, DL, D) if they are all present

Tue, 01/25/2005 - 17:52
elphel committed changes to the Elphel project fpga CVS:
Two bugs were discovered and fixed while testing the output data with a standard decoder, both related to replacing the predicted value with one of the 3 neighbours (L, DL, D) if they are all present

[fpga] By elphel: Two bugs fixed that were discovered when feeding the output to the standard decoder. One - shift by 128 for both Y and C (on the input of forward DCT and output of the inverse DCT), the other - dc_predict was providing 2's complement...

Tue, 01/25/2005 - 17:47
elphel committed changes to the Elphel project fpga CVS:
Two bugs fixed that were discovered when feeding the output to the standard decoder. One - shift by 128 for both Y and C (on the input of forward DCT and output of the inverse DCT), the other - dc_predict was providing 2's complement output, and dct_encode expected sign+magnitude

[fpga] By elphel: Added register level to ease timing

Tue, 01/25/2005 - 17:40
elphel committed changes to the Elphel project fpga CVS:
Added register level to ease timing

[fpga] By elphel: fixed some bugs while running the output data from the FPGA thropugh the actual decoder

Sat, 01/22/2005 - 01:11
elphel committed changes to the Elphel project fpga CVS:
fixed some bugs while running the output data from the FPGA thropugh the actual decoder

[fpga] By elphel: Made the index to Huffman group conversion match Theora codecs - there was an error in documentation

Wed, 01/19/2005 - 18:11
elphel committed changes to the Elphel project fpga CVS:
Made the index to Huffman group conversion match Theora codecs - there was an error in documentation

[fpga] By elphel: implemented debug mode (serial readout of internal data registers). Unfortunately synthesis tool gives internal errors on the attempts to directly access registers through hieararchy so all the data should be passed through the chain...

Mon, 01/17/2005 - 10:50
elphel committed changes to the Elphel project fpga CVS:
implemented debug mode (serial readout of internal data registers). Unfortunately synthesis tool gives internal errors on the attempts to directly access registers through hieararchy so all the data should be passed through the chain of modules I/Os

[fpga] By elphel: put TIG on data bus after making sure no module uses it first cycle of the 2-cycle window.

Mon, 01/17/2005 - 10:46
elphel committed changes to the Elphel project fpga CVS:
put TIG on data bus after making sure no module uses it first cycle of the 2-cycle window.

[fpga] By elphel: added support for the debug mode simulation

Mon, 01/17/2005 - 10:43
elphel committed changes to the Elphel project fpga CVS:
added support for the debug mode simulation

[fpga] By elphel: moved table address write strobe so no data will be used in the first of the 2-cycles long valid window to be able to ease data bus timing

Mon, 01/17/2005 - 10:42
elphel committed changes to the Elphel project fpga CVS:
moved table address write strobe so no data will be used in the first of the 2-cycles long valid window to be able to ease data bus timing

[fpga] By elphel: moved PIO data read strobe so no data will be used in the first of the 2-cycles long valid window to be able to ease data bus timing

Mon, 01/17/2005 - 10:41
elphel committed changes to the Elphel project fpga CVS:
moved PIO data read strobe so no data will be used in the first of the 2-cycles long valid window to be able to ease data bus timing

[fpga] By elphel: moved table address write strobe so mno data will be used in the first of the 2-cycles long valid window to be able to ease data bus timing

Mon, 01/17/2005 - 10:40
elphel committed changes to the Elphel project fpga CVS:
moved table address write strobe so mno data will be used in the first of the 2-cycles long valid window to be able to ease data bus timing

[fpga] By elphel: added debug mode

Mon, 01/17/2005 - 10:38
elphel committed changes to the Elphel project fpga CVS:
added debug mode

[fpga] By elphel: moved strobes that use PIO data 1 cycle behind to easy timing on data bus

Mon, 01/17/2005 - 10:36
elphel committed changes to the Elphel project fpga CVS:
moved strobes that use PIO data 1 cycle behind to easy timing on data bus

[fpga] By elphel: added debug mode

Mon, 01/17/2005 - 10:34
elphel committed changes to the Elphel project fpga CVS:
added debug mode

[fpga] By elphel: added shift registers to read debug data out

Mon, 01/17/2005 - 10:33
elphel committed changes to the Elphel project fpga CVS:
added shift registers to read debug data out

[fpga] By elphel: added signals for debugging purposes, cleaned up some code

Mon, 01/17/2005 - 10:32
elphel committed changes to the Elphel project fpga CVS:
added signals for debugging purposes, cleaned up some code

[fpga] By elphel: added debug mode

Mon, 01/17/2005 - 10:30
elphel committed changes to the Elphel project fpga CVS:
added debug mode

[fpga] By elphel: moved table address write strobe

Mon, 01/17/2005 - 10:29
elphel committed changes to the Elphel project fpga CVS:
moved table address write strobe

[fpga] By elphel: added debug signals

Mon, 01/17/2005 - 10:28
elphel committed changes to the Elphel project fpga CVS:
added debug signals

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