[fpga] By elphel: initial release - x333 FPGA interface description
elphel committed changes to the Elphel project fpga CVS:
initial release - x333 FPGA interface description
initial release - x333 FPGA interface description
- Modified x333_interface rev1.1 - added none, removed none
[fpga] By elphel: Replaced primitive that does not exist in Spartan 3 with the generic model
elphel committed changes to the Elphel project fpga CVS:
Replaced primitive that does not exist in Spartan 3 with the generic model
Replaced primitive that does not exist in Spartan 3 with the generic model
- Modified reorder_hilbert.v rev1.2 - added 38 lines, removed one line
[fpga] By elphel: reduced the table memory input width to resolve conflict with embedded multipliers
elphel committed changes to the Elphel project fpga CVS:
reduced the table memory input width to resolve conflict with embedded multipliers
reduced the table memory input width to resolve conflict with embedded multipliers
- Modified qdeq.v rev1.5 - added 26 lines, removed none
[fpga] By elphel: fixed dqs_re timing
elphel committed changes to the Elphel project fpga CVS:
fixed dqs_re timing
fixed dqs_re timing
- Modified mcontr_tok_rd.v rev1.3 - added 9 lines, removed 13 lines
[fpga] By elphel: fixed syntax error
elphel committed changes to the Elphel project fpga CVS:
fixed syntax error
fixed syntax error
- Modified mcontr_tokens.v rev1.2 - added 2 lines, removed 2 lines
[fpga] By elphel: Implemented clock phase control in the header file, fixed dqs_re timing
elphel committed changes to the Elphel project fpga CVS:
Implemented clock phase control in the header file, fixed dqs_re timing
Implemented clock phase control in the header file, fixed dqs_re timing
- Modified mcontr_tiles20x20_rd.v rev1.2 - added 6 lines, removed 3 lines
[fpga] By elphel: Implemented clock phase control in the header file, fixed dqs_re timing
elphel committed changes to the Elphel project fpga CVS:
Implemented clock phase control in the header file, fixed dqs_re timing
Implemented clock phase control in the header file, fixed dqs_re timing
- Modified mcontr_line512_rd.v rev1.2 - added 5 lines, removed 3 lines
[fpga] By elphel: Implemented clock phase control in the header file
elphel committed changes to the Elphel project fpga CVS:
Implemented clock phase control in the header file
Implemented clock phase control in the header file
- Modified mcontr_frame_rd.v rev1.3 - added 20 lines, removed 9 lines
[fpga] By elphel: Implemented clock phase control in the header file, added output
elphel committed changes to the Elphel project fpga CVS:
Implemented clock phase control in the header file, added output
Implemented clock phase control in the header file, added output
- Modified mcontr_frame_wr.v rev1.3 - added 22 lines, removed 6 lines
[fpga] By elphel: added missing register declaration
elphel committed changes to the Elphel project fpga CVS:
added missing register declaration
added missing register declaration
- Modified mcontr_cmd.v rev1.2 - added one line, removed none
[fpga] By elphel: provided additional outputs, fixed dqs_re timing
elphel committed changes to the Elphel project fpga CVS:
provided additional outputs, fixed dqs_re timing
provided additional outputs, fixed dqs_re timing
- Modified mcontr_8chn.v rev1.2 - added 21 lines, removed 4 lines
[fpga] By elphel: Replaced library element nonexestent in Spartan3 with generic behavioral module
elphel committed changes to the Elphel project fpga CVS:
Replaced library element nonexestent in Spartan3 with generic behavioral module
Replaced library element nonexestent in Spartan3 with generic behavioral module
- Modified macros333.v rev1.2 - added 29 lines, removed 2 lines
[fpga] By elphel: comment syntax error
elphel committed changes to the Elphel project fpga CVS:
comment syntax error
comment syntax error
- Modified fdct_1d.v rev1.4 - added one line, removed one line
[fpga] By elphel: New FPGA pinout for rev B
elphel committed changes to the Elphel project fpga CVS:
New FPGA pinout for rev B
New FPGA pinout for rev B
- Modified x333.v rev1.1 - added 6 lines, removed 2 lines
[fpga] By elphel: initial release, module combining all the Theora encoding
elphel committed changes to the Elphel project fpga CVS:
initial release, module combining all the Theora encoding
initial release, module combining all the Theora encoding
- Modified compressor_all.v rev1.1 - added none, removed none
[fpga] By elphel: Initial release of the files, modified from original version for 313/333 cameras working in JPEG mode
elphel committed changes to the Elphel project fpga CVS:
Initial release of the files, modified from original version for 313/333 cameras working in JPEG mode
Initial release of the files, modified from original version for 313/333 cameras working in JPEG mode
- Modified color_proc333t.v rev1.1 - added none, removed none
- Modified csconvert333.v rev1.1 - added none, removed none
- Modified defines333.vh rev1.1 - added none, removed none
- Modified dma_fifo333.v rev1.1 - added none, removed none
- Modified interrupts333t.v rev1.1 - added none, removed none
- Modified ioports333t.v rev1.1 - added none, removed none
- Modified sdram_phase.v rev1.1 - added none, removed none
- Modified sensdcclk333.v rev1.1 - added none, removed none
- Modified sensorpix333t.v rev1.1 - added none, removed none
[fpga] By elphel: provided "done" output
elphel committed changes to the Elphel project fpga CVS:
provided "done" output
provided "done" output
- Modified compressor_two.v rev1.2 - added 5 lines, removed 2 lines
[fpga] By elphel: Implemented clock phase control in the header file, reduced block RAM width to 18 (from 36) to resolve conflicts with embedded multipliers
elphel committed changes to the Elphel project fpga CVS:
Implemented clock phase control in the header file, reduced block RAM width to 18 (from 36) to resolve conflicts with embedded multipliers
Implemented clock phase control in the header file, reduced block RAM width to 18 (from 36) to resolve conflicts with embedded multipliers
- Modified compressor_one.v rev1.3 - added 114 lines, removed 12 lines
[fpga] By elphel: Implemented clock phase control in the header file
elphel committed changes to the Elphel project fpga CVS:
Implemented clock phase control in the header file
Implemented clock phase control in the header file
- Modified channel2.v rev1.2 - added 16 lines, removed 6 lines
[fpga] By elphel: added "done" output
elphel committed changes to the Elphel project fpga CVS:
added "done" output
added "done" output
- Modified bit_packager.v rev1.2 - added 6 lines, removed one line
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