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[fpga] By spectr_rain: fork 333 jpeg code with USB core

Elphel CVS logs - Tue, 04/25/2006 - 21:18
spectr_rain committed changes to the Elphel project fpga CVS:
fork 333 jpeg code with USB core

[fpga] By spectr_rain: fork 333 jpeg code with USB core

Elphel CVS logs - Tue, 04/25/2006 - 21:16
spectr_rain committed changes to the Elphel project fpga CVS:
fork 333 jpeg code with USB core

[fpga] By spectr_rain: fork 333 jpeg code with USB core

Elphel CVS logs - Tue, 04/25/2006 - 20:36
spectr_rain committed changes to the Elphel project fpga CVS:
fork 333 jpeg code with USB core

[fpga] By elphel: outputs from XIlinx tools running on the design

Elphel CVS logs - Thu, 03/17/2005 - 23:00
elphel committed changes to the Elphel project fpga CVS:
outputs from XIlinx tools running on the design

[fpga] By elphel: project file for Xilinx ISE

Elphel CVS logs - Thu, 03/17/2005 - 22:59
elphel committed changes to the Elphel project fpga CVS:
project file for Xilinx ISE

[fpga] By elphel: rev 03330026

Elphel CVS logs - Thu, 03/10/2005 - 22:40
elphel committed changes to the Elphel project fpga CVS:
rev 03330026

[fpga] By elphel: Cumulative bug fixes to FPGA rev 03330021.

Elphel CVS logs - Sat, 03/05/2005 - 16:56
elphel committed changes to the Elphel project fpga CVS:
Cumulative bug fixes to FPGA rev 03330021.

[fpga] By elphel: bug fix in mcontr_tok_rd.v

Elphel CVS logs - Wed, 02/23/2005 - 14:23
elphel committed changes to the Elphel project fpga CVS:
bug fix in mcontr_tok_rd.v

[fpga] By elphel: FPGA image - rev 0333001b

Elphel CVS logs - Sat, 02/19/2005 - 16:18
elphel committed changes to the Elphel project fpga CVS:
FPGA image - rev 0333001b

[fpga] By elphel: fixed bug that prepared all quantization tables the same (it was dicovered by color blocks in the decoder output, removed some already commented out code

Elphel CVS logs - Tue, 01/25/2005 - 18:14
elphel committed changes to the Elphel project fpga CVS:
fixed bug that prepared all quantization tables the same (it was dicovered by color blocks in the decoder output, removed some already commented out code

[fpga] By elphel: added more test output dump files (to compare with decoder) changed quantization values

Elphel CVS logs - Tue, 01/25/2005 - 18:11
elphel committed changes to the Elphel project fpga CVS:
added more test output dump files (to compare with decoder) changed quantization values

[fpga] By elphel: Changed some TIG (timing ignore) constraints to double cycle ones, added more of such (acually easin constraints)

Elphel CVS logs - Tue, 01/25/2005 - 18:08
elphel committed changes to the Elphel project fpga CVS:
Changed some TIG (timing ignore) constraints to double cycle ones, added more of such (acually easin constraints)

[fpga] By elphel: Swapped output bytes, changed Rev number and copyright dates

Elphel CVS logs - Tue, 01/25/2005 - 18:05
elphel committed changes to the Elphel project fpga CVS:
Swapped output bytes, changed Rev number and copyright dates

[fpga] By elphel: moved 2's complement -> {sign,abs} conversion on the output here from the module above

Elphel CVS logs - Tue, 01/25/2005 - 17:56
elphel committed changes to the Elphel project fpga CVS:
moved 2's complement -> {sign,abs} conversion on the output here from the module above

[fpga] By elphel: Two bugs were discovered and fixed while testing the output data with a standard decoder, both related to replacing the predicted value with one of the 3 neighbours (L, DL, D) if they are all present

Elphel CVS logs - Tue, 01/25/2005 - 17:52
elphel committed changes to the Elphel project fpga CVS:
Two bugs were discovered and fixed while testing the output data with a standard decoder, both related to replacing the predicted value with one of the 3 neighbours (L, DL, D) if they are all present

[fpga] By elphel: Two bugs fixed that were discovered when feeding the output to the standard decoder. One - shift by 128 for both Y and C (on the input of forward DCT and output of the inverse DCT), the other - dc_predict was providing 2's complement...

Elphel CVS logs - Tue, 01/25/2005 - 17:47
elphel committed changes to the Elphel project fpga CVS:
Two bugs fixed that were discovered when feeding the output to the standard decoder. One - shift by 128 for both Y and C (on the input of forward DCT and output of the inverse DCT), the other - dc_predict was providing 2's complement output, and dct_encode expected sign+magnitude

[fpga] By elphel: Added register level to ease timing

Elphel CVS logs - Tue, 01/25/2005 - 17:40
elphel committed changes to the Elphel project fpga CVS:
Added register level to ease timing

[fpga] By elphel: fixed some bugs while running the output data from the FPGA thropugh the actual decoder

Elphel CVS logs - Sat, 01/22/2005 - 01:11
elphel committed changes to the Elphel project fpga CVS:
fixed some bugs while running the output data from the FPGA thropugh the actual decoder

[fpga] By elphel: Made the index to Huffman group conversion match Theora codecs - there was an error in documentation

Elphel CVS logs - Wed, 01/19/2005 - 18:11
elphel committed changes to the Elphel project fpga CVS:
Made the index to Huffman group conversion match Theora codecs - there was an error in documentation

[fpga] By elphel: implemented debug mode (serial readout of internal data registers). Unfortunately synthesis tool gives internal errors on the attempts to directly access registers through hieararchy so all the data should be passed through the chain...

Elphel CVS logs - Mon, 01/17/2005 - 10:50
elphel committed changes to the Elphel project fpga CVS:
implemented debug mode (serial readout of internal data registers). Unfortunately synthesis tool gives internal errors on the attempts to directly access registers through hieararchy so all the data should be passed through the chain of modules I/Os

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