AndreyFilippov committed changes to the Elphel git project :
commands and status for LWIR/VOSPI, exported to C

AndreyFilippov committed changes to the Elphel git project :
split file by modules

AndreyFilippov committed changes to the Elphel git project :
cosmetic

AndreyFilippov committed changes to the Elphel git project :
modifying TCL scripts for Xilinx tools to support LWIR sensors

AndreyFilippov committed changes to the Elphel git project :
connecting LWIR sensors to FPGA code

AndreyFilippov committed changes to the Elphel git project :
simulation module for LWIR sensor

AndreyFilippov committed changes to the Elphel git project :
New modules for LWIR sensor

AndreyFilippov committed changes to the Elphel git project :
merged with lwir, tiff for both sensors

AndreyFilippov committed changes to the Elphel git project :
set to parallel

AndreyFilippov committed changes to the Elphel git project :
added implementation reports to git

AndreyFilippov committed changes to the Elphel git project :
reran, timing met

‎Additional manual setup for linux-elphel.project

← Older revision Revision as of 21:25, 4 April 2019 (3 intermediate revisions by the same user not shown)Line 75: Line 75:     After creating a new workspace with '''setup_eclipse.py''' it can be opened with Eclipse, the projects you plan to use have to be indexed (right-click on the project in the Navigator ⇒ Index ⇒ Rebuild. After creating a new workspace with '''setup_eclipse.py''' it can be opened with Eclipse, the projects you plan to use have to be indexed (right-click on the project in the Navigator ⇒ Index ⇒ Rebuild.  +=== Additional manual setup for linux-elphel.project===  +[[File:Eclipse_cdt.png|right|300px|frame|Adding ''linux/include/generated/autoconf.h'' entry to ''linux-elphel'' project properties]]  +Until we found a way how to set it automatically, the linux/include/generated/autoconf.h file has to be added to the project properties, as shown in the screenshot.     ==Initializing Eclipse Workspace for Existing (Cloned) Verilog Projects== ==Initializing Eclipse Workspace for Existing (Cloned) Verilog Projects== Andrey.filippov

Andrey.filippov uploaded File:Eclipse cdt.png

New page

== Licensing ==
{{GNU FDLv1.3 }} Andrey.filippov

AndreyFilippov committed changes to the Elphel git project :
more to ignore

AndreyFilippov committed changes to the Elphel git project :
Updated simulation code

AndreyFilippov committed changes to the Elphel git project :
removed possibility of conflicting mode bits

AndreyFilippov committed changes to the Elphel git project :
CRC for LWIR sensor

AndreyFilippov committed changes to the Elphel git project :
more data files/images

AndreyFilippov committed changes to the Elphel git project :
just comments

Oleg Dzhimiev committed changes to the Elphel git project :
removed double trigger for non-tiff formats