[fpga] By elphel: New FPGA pinout for rev B
elphel committed changes to the Elphel project fpga CVS:
New FPGA pinout for rev B
New FPGA pinout for rev B
- Modified x333.v rev1.1 - added 6 lines, removed 2 lines
[fpga] By elphel: initial release, module combining all the Theora encoding
elphel committed changes to the Elphel project fpga CVS:
initial release, module combining all the Theora encoding
initial release, module combining all the Theora encoding
- Modified compressor_all.v rev1.1 - added none, removed none
[fpga] By elphel: Initial release of the files, modified from original version for 313/333 cameras working in JPEG mode
elphel committed changes to the Elphel project fpga CVS:
Initial release of the files, modified from original version for 313/333 cameras working in JPEG mode
Initial release of the files, modified from original version for 313/333 cameras working in JPEG mode
- Modified color_proc333t.v rev1.1 - added none, removed none
- Modified csconvert333.v rev1.1 - added none, removed none
- Modified defines333.vh rev1.1 - added none, removed none
- Modified dma_fifo333.v rev1.1 - added none, removed none
- Modified interrupts333t.v rev1.1 - added none, removed none
- Modified ioports333t.v rev1.1 - added none, removed none
- Modified sdram_phase.v rev1.1 - added none, removed none
- Modified sensdcclk333.v rev1.1 - added none, removed none
- Modified sensorpix333t.v rev1.1 - added none, removed none
[fpga] By elphel: provided "done" output
elphel committed changes to the Elphel project fpga CVS:
provided "done" output
provided "done" output
- Modified compressor_two.v rev1.2 - added 5 lines, removed 2 lines
[fpga] By elphel: Implemented clock phase control in the header file, reduced block RAM width to 18 (from 36) to resolve conflicts with embedded multipliers
elphel committed changes to the Elphel project fpga CVS:
Implemented clock phase control in the header file, reduced block RAM width to 18 (from 36) to resolve conflicts with embedded multipliers
Implemented clock phase control in the header file, reduced block RAM width to 18 (from 36) to resolve conflicts with embedded multipliers
- Modified compressor_one.v rev1.3 - added 114 lines, removed 12 lines
[fpga] By elphel: Implemented clock phase control in the header file
elphel committed changes to the Elphel project fpga CVS:
Implemented clock phase control in the header file
Implemented clock phase control in the header file
- Modified channel2.v rev1.2 - added 16 lines, removed 6 lines
[fpga] By elphel: added "done" output
elphel committed changes to the Elphel project fpga CVS:
added "done" output
added "done" output
- Modified bit_packager.v rev1.2 - added 6 lines, removed one line
[fpga] By elphel: test fixture and data files for simulating compressor_two
elphel committed changes to the Elphel project fpga CVS:
test fixture and data files for simulating compressor_two
test fixture and data files for simulating compressor_two
- Modified compressor_two.tf rev1.1 - added none, removed none
- Modified hufftab80.dat rev1.1 - added none, removed none
- Modified tokens12_1st.dat rev1.1 - added none, removed none
[fpga] By elphel: test fixture for bit_packager.v
elphel committed changes to the Elphel project fpga CVS:
test fixture for bit_packager.v
test fixture for bit_packager.v
- Modified bit_packager.tf rev1.1 - added none, removed none
[fpga] By elphel: initial release of compressor_two that gets 12-bit "pore-tokens" from the frame memory in coded order, encodes them using Huffman tables and prepares for DMA output
elphel committed changes to the Elphel project fpga CVS:
initial release of compressor_two that gets 12-bit "pore-tokens" from the frame memory in coded order, encodes them using Huffman tables and prepares for DMA output
initial release of compressor_two that gets 12-bit "pore-tokens" from the frame memory in coded order, encodes them using Huffman tables and prepares for DMA output
- Modified bit_packager.v rev1.1 - added none, removed none
- Modified token_encode.v rev1.1 - added none, removed none
[fpga] By elphel: bug fixes to rev 03330025
elphel committed changes to the Elphel project fpga CVS:
bug fixes to rev 03330025
bug fixes to rev 03330025
- Modified compressor_two.v rev1.1 - added 9 lines, removed one line
[fpga] By elphel: data files for simulatin compressor_one
elphel committed changes to the Elphel project fpga CVS:
data files for simulatin compressor_one
data files for simulatin compressor_one
- Modified acdcscale.dat rev1.1 - added none, removed none
- Modified bms.dat rev1.1 - added none, removed none
[fpga] By elphel: several small universal modules
elphel committed changes to the Elphel project fpga CVS:
several small universal modules
several small universal modules
- Modified macros333.v rev1.1 - added none, removed none
[fpga] By elphel: removed obsolete comment
elphel committed changes to the Elphel project fpga CVS:
removed obsolete comment
removed obsolete comment
- Modified mcontr_tok_rd.v rev1.2 - added one line, removed one line
[fpga] By elphel: modified to match new compressor_one.v
elphel committed changes to the Elphel project fpga CVS:
modified to match new compressor_one.v
modified to match new compressor_one.v
- Modified compressor_one.tf rev1.2 - added 176 lines, removed 99 lines
[fpga] By elphel: included map table that stores 2 bits per 2x2 macroblocks (32x32 pixels) - skip (not code) and quality - one of two alternative table sets available in the same frame.
elphel committed changes to the Elphel project fpga CVS:
included map table that stores 2 bits per 2x2 macroblocks (32x32 pixels) - skip (not code) and quality - one of two alternative table sets available in the same frame.
included map table that stores 2 bits per 2x2 macroblocks (32x32 pixels) - skip (not code) and quality - one of two alternative table sets available in the same frame.
- Modified compressor_one.v rev1.2 - added 118 lines, removed 24 lines
[fpga] By elphel: Added more bits to the table address to be able to put more table in the same address space
elphel committed changes to the Elphel project fpga CVS:
Added more bits to the table address to be able to put more table in the same address space
Added more bits to the table address to be able to put more table in the same address space
- Modified qdeq.v rev1.4 - added 7 lines, removed 5 lines
[fpga] By elphel: error in comment fixed
elphel committed changes to the Elphel project fpga CVS:
error in comment fixed
error in comment fixed
- Modified qdeq.v rev1.3 - added one line, removed one line
[fpga] By elphel: copyright update, comments clean up
elphel committed changes to the Elphel project fpga CVS:
copyright update, comments clean up
copyright update, comments clean up
- Modified mcontr_frame_rd.v rev1.2 - added 2 lines, removed 4 lines
- Modified mcontr_frame_wr.v rev1.2 - added one line, removed one line
[fpga] By elphel: bug fix, and addition of the pre2_fo output (2 cycles ahead of the data out)
elphel committed changes to the Elphel project fpga CVS:
bug fix, and addition of the pre2_fo output (2 cycles ahead of the data out)
bug fix, and addition of the pre2_fo output (2 cycles ahead of the data out)
- Modified idct_2d.v rev1.4 - added 8 lines, removed 3 lines
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