[fpga] By elphel: implemented debug mode (serial readout of internal data registers). Unfortunately synthesis tool gives internal errors on the attempts to directly access registers through hieararchy so all the data should be passed through the chain...
elphel committed changes to the Elphel project fpga CVS:
implemented debug mode (serial readout of internal data registers). Unfortunately synthesis tool gives internal errors on the attempts to directly access registers through hieararchy so all the data should be passed through the chain of modules I/Os
implemented debug mode (serial readout of internal data registers). Unfortunately synthesis tool gives internal errors on the attempts to directly access registers through hieararchy so all the data should be passed through the chain of modules I/Os
- Modified x333.v rev1.8 - added 114 lines, removed 97 lines
[fpga] By elphel: put TIG on data bus after making sure no module uses it first cycle of the 2-cycle window.
elphel committed changes to the Elphel project fpga CVS:
put TIG on data bus after making sure no module uses it first cycle of the 2-cycle window.
put TIG on data bus after making sure no module uses it first cycle of the 2-cycle window.
- Modified x333.ucf rev1.2 - added one line, removed one line
[fpga] By elphel: added support for the debug mode simulation
elphel committed changes to the Elphel project fpga CVS:
added support for the debug mode simulation
added support for the debug mode simulation
- Modified x333t.tf rev1.4 - added 7 lines, removed 2 lines
- Modified x333t_parameters.tf rev1.3 - added 43 lines, removed 39 lines
- Modified x333t_tasks.tf rev1.4 - added 15 lines, removed 2 lines
[fpga] By elphel: moved table address write strobe so no data will be used in the first of the 2-cycles long valid window to be able to ease data bus timing
elphel committed changes to the Elphel project fpga CVS:
moved table address write strobe so no data will be used in the first of the 2-cycles long valid window to be able to ease data bus timing
moved table address write strobe so no data will be used in the first of the 2-cycles long valid window to be able to ease data bus timing
- Modified token_encode.v rev1.3 - added 6 lines, removed 3 lines
[fpga] By elphel: moved PIO data read strobe so no data will be used in the first of the 2-cycles long valid window to be able to ease data bus timing
elphel committed changes to the Elphel project fpga CVS:
moved PIO data read strobe so no data will be used in the first of the 2-cycles long valid window to be able to ease data bus timing
moved PIO data read strobe so no data will be used in the first of the 2-cycles long valid window to be able to ease data bus timing
- Modified sdram_phase.v rev1.2 - added 6 lines, removed 28 lines
[fpga] By elphel: moved table address write strobe so mno data will be used in the first of the 2-cycles long valid window to be able to ease data bus timing
elphel committed changes to the Elphel project fpga CVS:
moved table address write strobe so mno data will be used in the first of the 2-cycles long valid window to be able to ease data bus timing
moved table address write strobe so mno data will be used in the first of the 2-cycles long valid window to be able to ease data bus timing
- Modified qdeq.v rev1.6 - added 6 lines, removed 6 lines
[fpga] By elphel: added debug mode
elphel committed changes to the Elphel project fpga CVS:
added debug mode
added debug mode
- Modified mcontr_tok_wr.v rev1.5 - added 13 lines, removed none
[fpga] By elphel: moved strobes that use PIO data 1 cycle behind to easy timing on data bus
elphel committed changes to the Elphel project fpga CVS:
moved strobes that use PIO data 1 cycle behind to easy timing on data bus
moved strobes that use PIO data 1 cycle behind to easy timing on data bus
- Modified mcontr_cmd.v rev1.4 - added 6 lines, removed 11 lines
[fpga] By elphel: added debug mode
elphel committed changes to the Elphel project fpga CVS:
added debug mode
added debug mode
- Modified mcontr_8chn.v rev1.7 - added 23 lines, removed 7 lines
[fpga] By elphel: added shift registers to read debug data out
elphel committed changes to the Elphel project fpga CVS:
added shift registers to read debug data out
added shift registers to read debug data out
- Modified macros333.v rev1.3 - added 64 lines, removed 38 lines
[fpga] By elphel: added signals for debugging purposes, cleaned up some code
elphel committed changes to the Elphel project fpga CVS:
added signals for debugging purposes, cleaned up some code
added signals for debugging purposes, cleaned up some code
- Modified ioports333t.v rev1.3 - added 34 lines, removed 189 lines
[fpga] By elphel: added debug mode
elphel committed changes to the Elphel project fpga CVS:
added debug mode
added debug mode
- Modified defines333.vh rev1.3 - added one line, removed none
[fpga] By elphel: moved table address write strobe
elphel committed changes to the Elphel project fpga CVS:
moved table address write strobe
moved table address write strobe
- Modified compressor_two.v rev1.6 - added 6 lines, removed 4 lines
[fpga] By elphel: added debug signals
elphel committed changes to the Elphel project fpga CVS:
added debug signals
added debug signals
- Modified compressor_all.v rev1.6 - added 18 lines, removed none
[fpga] By elphel: moved table address strobe 1 cycle...
elphel committed changes to the Elphel project fpga CVS:
moved table address strobe 1 cycle added debug signals
moved table address strobe 1 cycle added debug signals
- Modified compressor_one.v rev1.6 - added 16 lines, removed 2 lines
[fpga] By elphel: comments updated
elphel committed changes to the Elphel project fpga CVS:
comments updated
comments updated
- Modified channel3.v rev1.3 - added one line, removed one line
[fpga] By elphel: not used anymore
elphel committed changes to the Elphel project fpga CVS:
not used anymore
not used anymore
- Modified dma_cntrl333.v rev1.2 - added none, removed none
[fpga] By elphel: fixed bug (signal between different clock domains) and added new status bit for troubleshooting
elphel committed changes to the Elphel project fpga CVS:
fixed bug (signal between different clock domains) and added new status bit for troubleshooting
fixed bug (signal between different clock domains) and added new status bit for troubleshooting
- Modified mcontr_8chn.v rev1.6 - added 40 lines, removed 2 lines
- Modified x333.v rev1.7 - added 6 lines, removed 3 lines
[fpga] By elphel: restored lost status bit that indicates that refresh is running - a way to find out that SDRAM is initialized
elphel committed changes to the Elphel project fpga CVS:
restored lost status bit that indicates that refresh is running - a way to find out that SDRAM is initialized
restored lost status bit that indicates that refresh is running - a way to find out that SDRAM is initialized
- Modified mcontr_8chn.v rev1.5 - added 5 lines, removed 3 lines
- Modified x333.v rev1.6 - added 46 lines, removed 44 lines
[fpga] By elphel: simulation bug fix
elphel committed changes to the Elphel project fpga CVS:
simulation bug fix
simulation bug fix
- Modified compressor_two.v rev1.5 - added one line, removed one line
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