[fpga] By elphel: added shift registers to read debug data out
elphel committed changes to the Elphel project fpga CVS:
added shift registers to read debug data out
added shift registers to read debug data out
- Modified macros333.v rev1.3 - added 64 lines, removed 38 lines
[fpga] By elphel: added signals for debugging purposes, cleaned up some code
elphel committed changes to the Elphel project fpga CVS:
added signals for debugging purposes, cleaned up some code
added signals for debugging purposes, cleaned up some code
- Modified ioports333t.v rev1.3 - added 34 lines, removed 189 lines
[fpga] By elphel: added debug mode
elphel committed changes to the Elphel project fpga CVS:
added debug mode
added debug mode
- Modified defines333.vh rev1.3 - added one line, removed none
[fpga] By elphel: moved table address write strobe
elphel committed changes to the Elphel project fpga CVS:
moved table address write strobe
moved table address write strobe
- Modified compressor_two.v rev1.6 - added 6 lines, removed 4 lines
[fpga] By elphel: added debug signals
elphel committed changes to the Elphel project fpga CVS:
added debug signals
added debug signals
- Modified compressor_all.v rev1.6 - added 18 lines, removed none
[fpga] By elphel: moved table address strobe 1 cycle...
elphel committed changes to the Elphel project fpga CVS:
moved table address strobe 1 cycle added debug signals
moved table address strobe 1 cycle added debug signals
- Modified compressor_one.v rev1.6 - added 16 lines, removed 2 lines
[fpga] By elphel: comments updated
elphel committed changes to the Elphel project fpga CVS:
comments updated
comments updated
- Modified channel3.v rev1.3 - added one line, removed one line
[fpga] By elphel: not used anymore
elphel committed changes to the Elphel project fpga CVS:
not used anymore
not used anymore
- Modified dma_cntrl333.v rev1.2 - added none, removed none
[fpga] By elphel: fixed bug (signal between different clock domains) and added new status bit for troubleshooting
elphel committed changes to the Elphel project fpga CVS:
fixed bug (signal between different clock domains) and added new status bit for troubleshooting
fixed bug (signal between different clock domains) and added new status bit for troubleshooting
- Modified mcontr_8chn.v rev1.6 - added 40 lines, removed 2 lines
- Modified x333.v rev1.7 - added 6 lines, removed 3 lines
[fpga] By elphel: restored lost status bit that indicates that refresh is running - a way to find out that SDRAM is initialized
elphel committed changes to the Elphel project fpga CVS:
restored lost status bit that indicates that refresh is running - a way to find out that SDRAM is initialized
restored lost status bit that indicates that refresh is running - a way to find out that SDRAM is initialized
- Modified mcontr_8chn.v rev1.5 - added 5 lines, removed 3 lines
- Modified x333.v rev1.6 - added 46 lines, removed 44 lines
[fpga] By elphel: simulation bug fix
elphel committed changes to the Elphel project fpga CVS:
simulation bug fix
simulation bug fix
- Modified compressor_two.v rev1.5 - added one line, removed one line
[fpga] By elphel: chip pinout on the model 333 PCB and timimng constraints
elphel committed changes to the Elphel project fpga CVS:
chip pinout on the model 333 PCB and timimng constraints
chip pinout on the model 333 PCB and timimng constraints
- Modified x333.ucf rev1.1 - added none, removed none
[fpga] By elphel: new rev number, made changes needed for moving some modules to different clock phases
elphel committed changes to the Elphel project fpga CVS:
new rev number, made changes needed for moving some modules to different clock phases
new rev number, made changes needed for moving some modules to different clock phases
- Modified x333.v rev1.5 - added 14 lines, removed 2 lines
[fpga] By elphel: added possibility to save generated tables and data fro comparison wity the actual hardware
elphel committed changes to the Elphel project fpga CVS:
added possibility to save generated tables and data fro comparison wity the actual hardware
added possibility to save generated tables and data fro comparison wity the actual hardware
- Modified x333t.tf rev1.3 - added 150 lines, removed 42 lines
- Modified x333t_tasks.tf rev1.3 - added 296 lines, removed 53 lines
[fpga] By elphel: bug fix, reduced table write data width, moved clock phase
elphel committed changes to the Elphel project fpga CVS:
bug fix, reduced table write data width, moved clock phase
bug fix, reduced table write data width, moved clock phase
- Modified token_encode.v rev1.2 - added 25 lines, removed 4 lines
[fpga] By elphel: changes caused by spreading modules between clock phases to reduce possible ground bounce and interference (channel 7 - read tokens from SDRAM moved)
elphel committed changes to the Elphel project fpga CVS:
changes caused by spreading modules between clock phases to reduce possible ground bounce and interference (channel 7 - read tokens from SDRAM moved)
changes caused by spreading modules between clock phases to reduce possible ground bounce and interference (channel 7 - read tokens from SDRAM moved)
- Modified mcontr_8chn.v rev1.4 - added 22 lines, removed 7 lines
[fpga] By elphel: changes caused by spreading modules between clock phases to reduce possible ground bounce and interference
elphel committed changes to the Elphel project fpga CVS:
changes caused by spreading modules between clock phases to reduce possible ground bounce and interference
changes caused by spreading modules between clock phases to reduce possible ground bounce and interference
- Modified mcontr_tok_rd.v rev1.6 - added 20 lines, removed 8 lines
[fpga] By elphel: just note in comments to verify the DCT pipe after changing clock phases
elphel committed changes to the Elphel project fpga CVS:
just note in comments to verify the DCT pipe after changing clock phases
just note in comments to verify the DCT pipe after changing clock phases
- Modified compressor_one.v rev1.5 - added 2 lines, removed one line
[fpga] By elphel: changes caused by spreading modules between clock phases to reduce possible ground bounce and interference
elphel committed changes to the Elphel project fpga CVS:
changes caused by spreading modules between clock phases to reduce possible ground bounce and interference
changes caused by spreading modules between clock phases to reduce possible ground bounce and interference
- Modified compressor_two.v rev1.4 - added 82 lines, removed 26 lines
[fpga] By elphel: changes caused by spreading modules between clock phases to reduce possible ground bounce and interference
elphel committed changes to the Elphel project fpga CVS:
changes caused by spreading modules between clock phases to reduce possible ground bounce and interference
changes caused by spreading modules between clock phases to reduce possible ground bounce and interference
- Modified compressor_all.v rev1.5 - added 33 lines, removed 8 lines
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