[fpga] By elphel: FPGA image - rev 0333001b
elphel committed changes to the Elphel project fpga CVS:
FPGA image - rev 0333001b
FPGA image - rev 0333001b
- Modified x333.bit rev1.1 - added none, removed none
[fpga] By elphel: fixed bug that prepared all quantization tables the same (it was dicovered by color blocks in the decoder output, removed some already commented out code
elphel committed changes to the Elphel project fpga CVS:
fixed bug that prepared all quantization tables the same (it was dicovered by color blocks in the decoder output, removed some already commented out code
fixed bug that prepared all quantization tables the same (it was dicovered by color blocks in the decoder output, removed some already commented out code
- Modified x333t_tasks.tf rev1.5 - added 3 lines, removed 34 lines
[fpga] By elphel: added more test output dump files (to compare with decoder) changed quantization values
elphel committed changes to the Elphel project fpga CVS:
added more test output dump files (to compare with decoder) changed quantization values
added more test output dump files (to compare with decoder) changed quantization values
- Modified x333t.tf rev1.5 - added 95 lines, removed 9 lines
[fpga] By elphel: Changed some TIG (timing ignore) constraints to double cycle ones, added more of such (acually easin constraints)
elphel committed changes to the Elphel project fpga CVS:
Changed some TIG (timing ignore) constraints to double cycle ones, added more of such (acually easin constraints)
Changed some TIG (timing ignore) constraints to double cycle ones, added more of such (acually easin constraints)
- Modified x333.ucf rev1.3 - added 25 lines, removed 6 lines
[fpga] By elphel: Swapped output bytes, changed Rev number and copyright dates
elphel committed changes to the Elphel project fpga CVS:
Swapped output bytes, changed Rev number and copyright dates
Swapped output bytes, changed Rev number and copyright dates
- Modified x333.v rev1.9 - added 6 lines, removed 5 lines
[fpga] By elphel: moved 2's complement -> {sign,abs} conversion on the output here from the module above
elphel committed changes to the Elphel project fpga CVS:
moved 2's complement -> {sign,abs} conversion on the output here from the module above
moved 2's complement -> {sign,abs} conversion on the output here from the module above
- Modified dc_predict.v rev1.3 - added 9 lines, removed one line
[fpga] By elphel: Two bugs were discovered and fixed while testing the output data with a standard decoder, both related to replacing the predicted value with one of the 3 neighbours (L, DL, D) if they are all present
elphel committed changes to the Elphel project fpga CVS:
Two bugs were discovered and fixed while testing the output data with a standard decoder, both related to replacing the predicted value with one of the 3 neighbours (L, DL, D) if they are all present
Two bugs were discovered and fixed while testing the output data with a standard decoder, both related to replacing the predicted value with one of the 3 neighbours (L, DL, D) if they are all present
- Modified dc_predict_calc.v rev1.2 - added 16 lines, removed 7 lines
[fpga] By elphel: Two bugs fixed that were discovered when feeding the output to the standard decoder. One - shift by 128 for both Y and C (on the input of forward DCT and output of the inverse DCT), the other - dc_predict was providing 2's complement...
elphel committed changes to the Elphel project fpga CVS:
Two bugs fixed that were discovered when feeding the output to the standard decoder. One - shift by 128 for both Y and C (on the input of forward DCT and output of the inverse DCT), the other - dc_predict was providing 2's complement output, and dct_encode expected sign+magnitude
Two bugs fixed that were discovered when feeding the output to the standard decoder. One - shift by 128 for both Y and C (on the input of forward DCT and output of the inverse DCT), the other - dc_predict was providing 2's complement output, and dct_encode expected sign+magnitude
- Modified compressor_one.v rev1.7 - added 25 lines, removed 7 lines
[fpga] By elphel: Added register level to ease timing
elphel committed changes to the Elphel project fpga CVS:
Added register level to ease timing
Added register level to ease timing
- Modified channel0.v rev1.3 - added 13 lines, removed 8 lines
- Modified channel1.v rev1.2 - added 13 lines, removed 10 lines
[fpga] By elphel: fixed some bugs while running the output data from the FPGA thropugh the actual decoder
elphel committed changes to the Elphel project fpga CVS:
fixed some bugs while running the output data from the FPGA thropugh the actual decoder
fixed some bugs while running the output data from the FPGA thropugh the actual decoder
- Modified compressor_two.v rev1.8 - added 73 lines, removed 24 lines
- Modified token_encode.v rev1.4 - added 81 lines, removed 10 lines
[fpga] By elphel: Made the index to Huffman group conversion match Theora codecs - there was an error in documentation
elphel committed changes to the Elphel project fpga CVS:
Made the index to Huffman group conversion match Theora codecs - there was an error in documentation
Made the index to Huffman group conversion match Theora codecs - there was an error in documentation
- Modified compressor_two.v rev1.7 - added 12 lines, removed 5 lines
[fpga] By elphel: implemented debug mode (serial readout of internal data registers). Unfortunately synthesis tool gives internal errors on the attempts to directly access registers through hieararchy so all the data should be passed through the chain...
elphel committed changes to the Elphel project fpga CVS:
implemented debug mode (serial readout of internal data registers). Unfortunately synthesis tool gives internal errors on the attempts to directly access registers through hieararchy so all the data should be passed through the chain of modules I/Os
implemented debug mode (serial readout of internal data registers). Unfortunately synthesis tool gives internal errors on the attempts to directly access registers through hieararchy so all the data should be passed through the chain of modules I/Os
- Modified x333.v rev1.8 - added 114 lines, removed 97 lines
[fpga] By elphel: put TIG on data bus after making sure no module uses it first cycle of the 2-cycle window.
elphel committed changes to the Elphel project fpga CVS:
put TIG on data bus after making sure no module uses it first cycle of the 2-cycle window.
put TIG on data bus after making sure no module uses it first cycle of the 2-cycle window.
- Modified x333.ucf rev1.2 - added one line, removed one line
[fpga] By elphel: added support for the debug mode simulation
elphel committed changes to the Elphel project fpga CVS:
added support for the debug mode simulation
added support for the debug mode simulation
- Modified x333t.tf rev1.4 - added 7 lines, removed 2 lines
- Modified x333t_parameters.tf rev1.3 - added 43 lines, removed 39 lines
- Modified x333t_tasks.tf rev1.4 - added 15 lines, removed 2 lines
[fpga] By elphel: moved table address write strobe so no data will be used in the first of the 2-cycles long valid window to be able to ease data bus timing
elphel committed changes to the Elphel project fpga CVS:
moved table address write strobe so no data will be used in the first of the 2-cycles long valid window to be able to ease data bus timing
moved table address write strobe so no data will be used in the first of the 2-cycles long valid window to be able to ease data bus timing
- Modified token_encode.v rev1.3 - added 6 lines, removed 3 lines
[fpga] By elphel: moved PIO data read strobe so no data will be used in the first of the 2-cycles long valid window to be able to ease data bus timing
elphel committed changes to the Elphel project fpga CVS:
moved PIO data read strobe so no data will be used in the first of the 2-cycles long valid window to be able to ease data bus timing
moved PIO data read strobe so no data will be used in the first of the 2-cycles long valid window to be able to ease data bus timing
- Modified sdram_phase.v rev1.2 - added 6 lines, removed 28 lines
[fpga] By elphel: moved table address write strobe so mno data will be used in the first of the 2-cycles long valid window to be able to ease data bus timing
elphel committed changes to the Elphel project fpga CVS:
moved table address write strobe so mno data will be used in the first of the 2-cycles long valid window to be able to ease data bus timing
moved table address write strobe so mno data will be used in the first of the 2-cycles long valid window to be able to ease data bus timing
- Modified qdeq.v rev1.6 - added 6 lines, removed 6 lines
[fpga] By elphel: added debug mode
elphel committed changes to the Elphel project fpga CVS:
added debug mode
added debug mode
- Modified mcontr_tok_wr.v rev1.5 - added 13 lines, removed none
[fpga] By elphel: moved strobes that use PIO data 1 cycle behind to easy timing on data bus
elphel committed changes to the Elphel project fpga CVS:
moved strobes that use PIO data 1 cycle behind to easy timing on data bus
moved strobes that use PIO data 1 cycle behind to easy timing on data bus
- Modified mcontr_cmd.v rev1.4 - added 6 lines, removed 11 lines
[fpga] By elphel: added debug mode
elphel committed changes to the Elphel project fpga CVS:
added debug mode
added debug mode
- Modified mcontr_8chn.v rev1.7 - added 23 lines, removed 7 lines
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