[fpga] By elphel: comments, changed signal
elphel committed changes to the Elphel project fpga CVS:
comments, changed signal
comments, changed signal
- Modified mcontr_8chn.v rev1.3 - added 10 lines, removed 6 lines
[fpga] By elphel: added sme debug output
elphel committed changes to the Elphel project fpga CVS:
added sme debug output
added sme debug output
- Modified ddr.v rev1.2 - added 4 lines, removed none
[fpga] By elphel: comments
elphel committed changes to the Elphel project fpga CVS:
comments
comments
- Modified compressor_two.v rev1.3 - added 3 lines, removed 3 lines
[fpga] By elphel: updated comments
elphel committed changes to the Elphel project fpga CVS:
updated comments
updated comments
- Modified compressor_one.v rev1.4 - added 7 lines, removed 6 lines
[fpga] By elphel: bug fix
elphel committed changes to the Elphel project fpga CVS:
bug fix
bug fix
- Modified compressor_all.v rev1.3 - added 18 lines, removed one line
[fpga] By elphel: bug fix
elphel committed changes to the Elphel project fpga CVS:
bug fix
bug fix
- Modified color_proc333t.v rev1.2 - added 18 lines, removed 5 lines
[fpga] By elphel: fixed misprint, updated copyright
elphel committed changes to the Elphel project fpga CVS:
fixed misprint, updated copyright
fixed misprint, updated copyright
- Modified channel3.v rev1.2 - added 26 lines, removed 26 lines
[fpga] By elphel: fixed misprint, updated copyright
elphel committed changes to the Elphel project fpga CVS:
fixed misprint, updated copyright
fixed misprint, updated copyright
- Modified channel0.v rev1.2 - added 24 lines, removed 23 lines
[fpga] By elphel: updated comments about table access register map
elphel committed changes to the Elphel project fpga CVS:
updated comments about table access register map
updated comments about table access register map
- Modified compressor_all.v rev1.2 - added 4 lines, removed 4 lines
[fpga] By elphel: removed unused outputs from sysinterface module
elphel committed changes to the Elphel project fpga CVS:
removed unused outputs from sysinterface module
removed unused outputs from sysinterface module
- Modified ioports333t.v rev1.2 - added 10 lines, removed 10 lines
[fpga] By elphel: minor cleanup and update
elphel committed changes to the Elphel project fpga CVS:
minor cleanup and update
minor cleanup and update
- Modified x333.v rev1.2 - added 32 lines, removed 25 lines
[fpga] By elphel: initial release - x333 FPGA interface description
elphel committed changes to the Elphel project fpga CVS:
initial release - x333 FPGA interface description
initial release - x333 FPGA interface description
- Modified x333_interface rev1.1 - added none, removed none
[fpga] By elphel: Replaced primitive that does not exist in Spartan 3 with the generic model
elphel committed changes to the Elphel project fpga CVS:
Replaced primitive that does not exist in Spartan 3 with the generic model
Replaced primitive that does not exist in Spartan 3 with the generic model
- Modified reorder_hilbert.v rev1.2 - added 38 lines, removed one line
[fpga] By elphel: reduced the table memory input width to resolve conflict with embedded multipliers
elphel committed changes to the Elphel project fpga CVS:
reduced the table memory input width to resolve conflict with embedded multipliers
reduced the table memory input width to resolve conflict with embedded multipliers
- Modified qdeq.v rev1.5 - added 26 lines, removed none
[fpga] By elphel: fixed dqs_re timing
elphel committed changes to the Elphel project fpga CVS:
fixed dqs_re timing
fixed dqs_re timing
- Modified mcontr_tok_rd.v rev1.3 - added 9 lines, removed 13 lines
[fpga] By elphel: fixed syntax error
elphel committed changes to the Elphel project fpga CVS:
fixed syntax error
fixed syntax error
- Modified mcontr_tokens.v rev1.2 - added 2 lines, removed 2 lines
[fpga] By elphel: Implemented clock phase control in the header file, fixed dqs_re timing
elphel committed changes to the Elphel project fpga CVS:
Implemented clock phase control in the header file, fixed dqs_re timing
Implemented clock phase control in the header file, fixed dqs_re timing
- Modified mcontr_tiles20x20_rd.v rev1.2 - added 6 lines, removed 3 lines
[fpga] By elphel: Implemented clock phase control in the header file, fixed dqs_re timing
elphel committed changes to the Elphel project fpga CVS:
Implemented clock phase control in the header file, fixed dqs_re timing
Implemented clock phase control in the header file, fixed dqs_re timing
- Modified mcontr_line512_rd.v rev1.2 - added 5 lines, removed 3 lines
[fpga] By elphel: Implemented clock phase control in the header file
elphel committed changes to the Elphel project fpga CVS:
Implemented clock phase control in the header file
Implemented clock phase control in the header file
- Modified mcontr_frame_rd.v rev1.3 - added 20 lines, removed 9 lines
[fpga] By elphel: Implemented clock phase control in the header file, added output
elphel committed changes to the Elphel project fpga CVS:
Implemented clock phase control in the header file, added output
Implemented clock phase control in the header file, added output
- Modified mcontr_frame_wr.v rev1.3 - added 22 lines, removed 6 lines
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